Master thesis defense by Arthur L. Bousquet

Miniaturized vertical interconnect access for quantum dot arrays

Thanks to their long coherence times, semiconductor spin qubits are one of the most promising platforms for quantum computing. Electrons are trapped inside semiconductors in quantum dots defined by metallic gate structures and their spin is used as a qubit. Various works during the last decade have shown that high fidelity single and two-qubit gates are possible and the field is now faced with another challenge: scaling up the number of qubits.
Going from a few qubits to devices with thousands of quantum dots involves rethinking completely the manufacturing process to switch to more reliable, industrial-grade, fabrication techniques that will allow scaling up device manufacturing.
In 2022, Ha et al. presented a new design platform for Si/SiGe qubits called single layer etch-defined gate electrode (SLEDGE). This fabrication process is designed to be compatible withindustrial CMOS processing and allows for a better management of the gate layers. A single gateelectrode layer is used; the gates are round which allows 2D quantum dot arrays to be made. Additionally, one or multiple “back end of line” structures create 2D fanout areas far away from the qubits for the gate electrodes.
Currently, SLEDGE devices use ohmic contacts made by ion implantation, this process is hard to localize and leads to electron reservoirs occupying large areas of the device. Another alternative exists and requires locally alloying the semiconductor with a metal. So far, this solution has never been incorporated into the SLEDGE process flow but could allow for smaller ohmic contacts, further improving device architecture. The aim of the thesis was to optimize various steps in the fabrication process with the end goal of making an improved SLEDGE device with miniaturized ohmic contacts.