Master thesis defense by Laura Navarro

SMART Slicing for T-States Optimization using Reinforcement Learning in Fault-Tolerant Quantum Circuits

Fault-tolerant quantum computation introduces a significant resource overhead, particularly for non-Clifford operations such as the T gate. Reducing the effective T-count is therefore an important step toward making these computations more practical. This thesis presents a Clifford+T circuit optimizer aimed at reducing this cost by detecting phase-gadget structures that can be replaced by lower-cost equivalent implementations. The method uses phase polynomials to represent suitable circuit regions, which are obtained by first dividing the circuit into Hadamard-free slices. A central contribution of this work is the SMART slicing strategy, which improves the selection of these regions and can reveal optimization opportunities hidden by naive slicing. The resulting slices are then processed by the full optimization pipeline, including reinforcement-learning-based transformations and circuit reconstruction. The optimizer is evaluated on benchmark circuits, achieving significant T-count reductions. The results also show that SMART slicing can provide additional improvements in selected cases. All reported optimized circuits were verified to be equivalent to the originals up to a global phase.